High speed computing devices are constructed by combining a number of integrated circuits (ICs) together to perform the required tasks. These integrated circuits are interconnected so that instructions and data are communicated between the ICs. The signal paths between the ICs are called transmission lines and the circuits that do the communicating are referred to as Input/Output (I/O) circuits. For signal quality reasons, a high speed transmission line needs to be terminated by a resistor load having the same resistance value as the characteristic impedance as the transmission line. This termination load dissipates power and therefore generates heat which is undesirable.
As circuit speeds and clock rates increase there is a need for I/O circuits that can handle these speeds but also have low power dissipation and can properly terminate a transmission line. There are two basic approaches to termination: Terminate at the driver (output) source and terminate at the destination (input) device. Source termination has low power dissipation properties. With source termination, receiving devices closest to the driver incur the longest latency due to the time it takes a signal to propagate to the end of the transmission line and be reflected back to the receiver. Terminating at the destination gives the best quality signal at the destination but suffers from a greater power dissipation than does source termination.
This invention is applicable to point to point communication which is used when the highest speeds are needed. Point to point means there is a driver at one end of the transmission line and a receiver at the other end. There are no receivers or drivers distributed along the transmission line. Any receivers or drivers distributed along the transmission line cause discontinuities which result in degraded signal quality so these are avoided at the highest speeds.
One typical prior attempt to provide high speed communications and low power termination of the transmission line is to use a lower power supply voltage of approximately 1.2v-1.8v and a reduced voltage swing in an otherwise 3.3v system. This reduces the voltage developed across the transmission line termination and therefore reduces the power dissipation in the termination device. An example of this approach to high speed I/O is the Gunning Transceiver Logic (GTL) configuration which is shown in FIG. 1.
FIG. 1 illustrates a NMOS driver circuit 101 located on a first IC 103 and an input circuit 105 located on a second IC 107. The two circuits 101 and 105 are connected by a transmission line 109 having an end termination load 111 and a source termination load 113. The transmission line 109 typically has a characteristic impedance of 50 ohms and therefore the terminating load 111 is designed to have the same resistance value (50 ohms).
In this circuit the GTL power components are:
1. Power dissipated by both termination resistors 113 and 111 (P.sub.term): ##EQU1## 2. Power dissipated by the NMOS driver circuit (P.sub.tx): ##EQU2## 3. Current delivered by each termination resistor (I.sub.dc): ##EQU3##
The 1/2 is to consider average power with the signal switching at a 50% duty cycle rate.
The power in the receivers of all approaches is similar and is dependent on the capacitive load and the circuit speed required.
Another approach is to use a receiver circuit, which is an inverter in which the switching threshold is skewed low to accommodate a signal voltage swing centered at approximately (1.2v+0.3v)/2=0.75v.
This second approach is illustrated in FIG. 2. This figure differs from FIG. 1 in that the receiving chip 201 has an inverting receiver 203. This type of receiver 203 is simpler than the receiver circuit 105 but the overall system has the same power dissipation as the system illustrated in FIG. 1.
For point to point applications these two schemes require a single termination resistor so for both the power results become: ##EQU4##
The problem with both of these approaches is the power dissipation in the termination loads is so great that the loads cannot be fabricated as part of the receiving IC, especially in high I/O count (500+I/O lines) applications. Because the termination loads have to be mounted off the receiving IC, there is a transmission line stub to make the connection to the load (resistor). This stub presents a discontinuity in the main transmission line and causes reflections which, at the circuit input, appear as glitches on the high or low level or as half level shoulders on incoming pulses. These glitches are illustrated in FIGS. 3 A-C.
FIG. 3A illustrates a glitch 301 on a low to high level incoming pulse 303. FIG. 3B illustrates a glitch 305 on a high to low level incoming pulse 307 and FIG. 3C illustrates a half level shoulder glitch 309 on a high to low level incoming pulse 311.
What is needed in the industry is a high speed I/O circuit that has a low power dissipation such that the transmission line termination can be fabricated as part of the receiving IC to eliminate impedance discontinuities and the associated glitches.